1. Field of the Invention
The invention relates to methods for modeling electric effects of interconnect parasitics in integrated circuits.
2. Background Art
The design of an integrated circuit occurs in several stages. As illustrated in FIG. 1, the design of the integrated circuit starts with drafting a specification of the intended functions of the integrated circuit (shown at 2). A logic design is then produced and optimized based on the functions described in the specification (shown at 4). For ultra large scale integration (ULSI), i.e., an integrated circuit consisting of millions of transistors, the logic design is described in many levels of abstraction to ensure an orderly and structured design process. Typically, the logic design is expressed as a set of interconnected blocks in a hierarchical structure, each block in the design hierarchy representing pieces of hardware ranging from simple logic gates to complete systems, e.g., microprocessors. A floor plan of the integrated circuit is created from the logic design (shown 6). The floor plan is transferred to a layout design system for placement and routing (shown at 8). xe2x80x9cPlacementxe2x80x9d is the process by which logic elements in the logic design are realized in the circuit elements of a physical implementation, and xe2x80x9croutingxe2x80x9d is the process by which metal interconnections are created between the circuit elements. After placement and routing, estimates of the parasitic impedances of the metal interconnections are made (xe2x80x9cextractedxe2x80x9d) to form an interconnect delay model (shown at 10). The signal path delays are then calculated using the interconnect delay model, and detailed timing analysis is performed to verify that the delay characteristics of the circuit satisfy specified design criteria (shown at 12). The design process is completed (shown at 14) if the delay characteristics of the circuit satisfy specified design criteria. If the delay characteristics of the circuit do not satisfy specified design criteria, the logic design is refined and the circuit is retested until the delay characteristics of the circuit satisfy the specified design criteria.
In deep submicron process technologies (0.35 xcexcm and below), interconnect delays dominate system performance. Therefore, accurate modeling of the parasitic effects, e.g., parasitic capacitances, associated with the interconnects is very important. The most accurate algorithm for extracting capacitance involves solving Laplace""s equation with boundary conditions numerically. See, for example, E. Dengi and R. Rohrer, xe2x80x9cBoundary Element Method Macromodels for 2-D Hierarchical Capacitance Extraction,xe2x80x9d Proc. of the 35th DAC, pp. 218-333, June 1998, W. Shi et al., xe2x80x9cA Fast Hierarchical Algorithm for 3-D Capacitance Extraction,xe2x80x9d Proc. of the 35th DAC, pp. 212-217, June 1998. This approach is, however, very slow and therefore not appropriate for computing the overall capacitance matrix of ULSI layout. Full-chip interconnect models are usually obtained using a layout parameter extraction tool which employs three-dimensional field solutions to create analytical model or lookup table models. These models in conjunction with layout pattern recognition algorithms are applied during run time to determine capacitance values. To ensure the quality of subsequent timing and signal integrity analyses, the extracted parasitic values have to be verified against some known xe2x80x9cgolden dataxe2x80x9d which are either results of three-dimensional field solutions or measured parasitic values. See, for example, P. Franzon et al., xe2x80x9cParasitic Extraction Accuracy; How much is enough?xe2x80x9d Proc. of the 36th DAC, pp. 429, June 1999. Once an extraction tool is validated, a flat, post-layout extraction is expected to produce reasonably accurate interconnect models.
Interconnect parasitics are not intentionally designed into a chip but rather are consequences of the layout and are usually degrading to the circuit performance. Thus modeling interconnect parasitics early in the design process, i.e., prior to completion of the physical design, is crucial to capturing major timing and noise problems. Initially, values of interconnect parasitics are computed based on a set of wire load models and Manhattan distances of the nets. Later in the design process, most blocks on the chip have either a partial layout view or an abstract view describing areas to be occupied by a certain level of metal. To achieve timing closure, a realistic estimation of the total capacitance for the nets must be determined. The total net capacitance is given by the following expression:                               C          T                =                              C            G                    +                                    ∑              i                        ⁢                          xe2x80x83                        ⁢                                          M                i                            ⁢                              C                C                i                                                                        (        1        )            
where Mi are Miller scaling factors, usually ranging from 0 to 2, CG is the capacitance to static nets (ground), and Cci are capacitances to switching nets (signal). In order to compute CT, it is necessary to distinguish between switching nets and static nets. Unfortunately, the switching information of every net is not known prior to completion of the physical design. Without switching information, performance analysis (timing, noise, etc.) has to be done under xe2x80x9cworst casexe2x80x9d assumptions. However, in hierarchical extraction, most extraction tools consider all unspecified nets static by default. As a result, the worst case conditions may not necessarily be captured, leading to significant errors in analysis results.
In one aspect, the invention relates to a method for extracting parasitic capacitance from an integrated circuit layout which comprises decomposing nets in the integrated circuit layout into conductive segments along two mutually perpendicular directions. The method further includes summing capacitances between the conductive segments in a selected net and the remaining conductive segments in the integrated circuit layout that are aligned with the conductive segments in the selected net and multiplying the sum by a scaling factor to obtain a first capacitance value. The method further includes summing capacitances between the conductive segments in the selected net and the remaining conductive segments in the integrated circuit layout that are transverse, to the conductive segments in the selected net to obtain a second capacitance value. The method further includes summing the first capacitance value and second capacitance value to obtain a total capacitance value for the selected net.
In another aspect, the invention relates to a method for extracting parasitic capacitance from an integrated circuit layout which comprises decomposing nets in the integrated circuit layout into conductive segments along two mutually perpendicular directions. The method further includes summing capacitances between the conductive segments in a selected net and the remaining conductive segments in the integrated circuit layout that are aligned with the conductive segments in the selected net and multiplying the sum by a first scaling factor to obtain a first capacitance value. The method further includes summing capacitances between the conductive segments in the selected net and the remaining conductive segments in the integrated circuit layout that are transverse to the conductive segments in the selected net and multiplying the sum by a second scaling factor to obtain a second capacitance value. The method further includes summing the first capacitance value and second capacitance value to obtain a total capacitance value for the selected net.
Other aspects and advantages of the invention will be apparent from the description which follows and the appended claims.